UNCLASSIFIED
TM-CAL-003
GPS-DISCIPLINED OSCILLATOR (GPSDO)
10 MHz Reference Oscillator Disciplined to GPS/UTC via Phase-Locked Loop
Prepared by: Mervyn Martin, KO6NNH
Merced, California  •  26 May 2026
Amateur Radio / Electronics — Not for commercial calibration use

Table of Contents

  1. Chapter 1 — General Information
  2. Chapter 2 — Theory of Operation
  3. Chapter 3 — Materials and Construction
  4. Chapter 4 — Assembly Procedures
  5. Chapter 5 — Calibration Procedure
  6. Chapter 6 — Tuning and Adjustment
  7. Chapter 7 — Verification
  8. Appendix A — Calculations and Formulas
  9. Appendix B — Example Results

CHAPTER 1 — GENERAL INFORMATION

1-1. SCOPE

This manual covers construction and calibration use of a GPS-Disciplined Oscillator (GPSDO) providing a 10 MHz sine or square wave reference traceable to UTC via GPS. The GPSDO provides better short-term stability than 1PPS alone and is suitable as a lab reference for all RF calibration work.

1-2. REFERENCES

  • TM-CAL-002: GPS 1PPS Timing Reference
  • u-blox NEO-M8N Integration Manual
  • Silicon Labs Si5351A Datasheet
  • Analog Devices AD9833 Datasheet

1-3. SAFETY

NOTEGPSDO construction involves 5 V DC circuits only. No shock hazard.
CAUTIONThe GPSDO output must be terminated in 50 Ω. Open-circuit or short-circuit output damages the Si5351 output stage.

CHAPTER 2 — THEORY OF OPERATION

2-1. GPSDO PRINCIPLE

A GPSDO phase-locks a voltage-controlled crystal oscillator (VCXO) or temperature-compensated crystal oscillator (TCXO) to the GPS 1PPS signal using a phase-locked loop (PLL) or proportional-integral (PI) control algorithm.

Long-term frequency accuracy follows GPS (≈10−12 relative). Short-term stability (seconds) follows the free-running crystal oscillator, which is better than GPS for short intervals due to GPS noise.

2-2. IMPLEMENTATION: NEO-M8N + Si5351

The Si5351A clock generator synthesizes multiple output frequencies from an onboard 25 MHz crystal. Output frequencies are set by integer and fractional division registers over I2C. The ESP32 microcontroller reads GPS NMEA data, monitors 1PPS, and adjusts Si5351 PLL registers to phase-lock the output.

GPSDO Performance (NEO-M8N + Si5351A, SW PLL)
ParameterValueNotes
Frequency range1 Hz – 160 MHzSi5351A spec
Output frequency (typical)10.000000 MHzAdjustable
Long-term accuracy<1×10−10GPS-limited
Short-term stability (1 s)≈10−9Crystal-limited
Output level~3 dBm into 50 ΩSi5351 CLK0
Lock time5–15 minutesAfter GPS position fix

CHAPTER 3 — MATERIALS AND CONSTRUCTION

3-1. BILL OF MATERIALS

GPSDO Components
QtyItemSpecification
1u-blox NEO-M8N GPS moduleWith UART and TIMEPULSE
1Si5351A clock breakoutAdafruit or equivalent, 25 MHz XTAL
1ESP32 development boardAny variant with I2C and UART
1Active GPS patch antennaMagnetic mount, 3.3 V bias
15 V / 500 mA supplyClean, low-ripple
1SMA panel connectorFor 10 MHz output
1Project enclosureDiecast aluminum preferred for RF shielding
4100 nF bypass capacitorsOn every power rail
110 μF electrolyticBulk bypass for ESP32 supply

3-2. WIRING

Connect NEO-M8N UART TX → ESP32 UART RX. Connect NEO-M8N TIMEPULSE → ESP32 GPIO (e.g., GPIO 4) with 100 Ω series resistor. Connect Si5351 SDA/SCL → ESP32 I2C (GPIO 21/22). Connect Si5351 CLK0 output → SMA panel connector via short 50 Ω trace.

CHAPTER 4 — ASSEMBLY PROCEDURES

  1. Verify all components with multimeter before assembly.
  2. Install ESP32 board on DIN rail or in enclosure, securing with 4 M3 screws.
  3. Mount Si5351 breakout board adjacent to ESP32. Keep I2C traces short (<5 cm).
  4. Mount NEO-M8N module. Route UART and TIMEPULSE connections to ESP32.
  5. Install SMA connector on enclosure panel. Solder short RG-174 pigtail from Si5351 CLK0 output to SMA center pin. Minimize trace length.
  6. Install GPS antenna SMA bulkhead connector on enclosure lid or side panel.
  7. Wire 5 V supply to all modules. Verify +5 V on each module before applying full power.
  8. Load ESP32 firmware (simple PLL algorithm: measure 1PPS → count Si5351 cycles → adjust frequency word in PI loop).
  9. Apply power. Observe serial debug output: GPS acquiring, then position fix, then TIMEPULSE valid, then PLL locking.
  10. Allow 15 minutes for full phase lock. Output frequency should stabilize to <1 Hz of 10.000000 MHz.

CHAPTER 5 — CALIBRATION PROCEDURE

5-1. INITIAL FREQUENCY CALIBRATION

  1. Connect GPSDO 10 MHz output to frequency counter via 50 Ω BNC cable.
  2. Allow GPSDO to lock completely (GPS fix acquired + 15 min warm-up).
  3. Measure output frequency. Should read 10.000000 ±0.010 MHz within 5 minutes of lock.
  4. If frequency is off by more than 1 Hz, check Si5351 crystal frequency setting in firmware. The on-board crystal may be 25.000 or 26.000 MHz; verify and update firmware constant.
  5. Monitor frequency for 30 minutes. Deviation from 10.000000 should be <1 Hz after full thermal stabilization.
  6. Record: frequency, GPS satellite count, ambient temperature.

5-2. LONG-TERM VERIFICATION

  1. Run GPSDO continuously for 24 hours.
  2. Record frequency every hour (automate with frequency counter if possible).
  3. Plot frequency vs. time. Drift >0.1 Hz over 24 hours indicates PLL loop filter or crystal aging issue.
  4. Compare to WWV at 10 MHz using zero-beat method (see TM-CAL-001). Agreement within 1 Hz confirms NIST traceability.

CHAPTER 6 — TUNING AND ADJUSTMENT

6-1. PLL LOOP FILTER TUNING

The PI control loop has two parameters: proportional gain (Kp) and integral gain (Ki). Too high Kp causes oscillation; too low causes slow lock. Start with Kp = 0.1 and Ki = 0.01, then increase Kp until oscillation appears, then back off 50%.

NOTEThe Si5351A frequency resolution is approximately 0.01 Hz at 10 MHz due to the 27-bit PLL multisynth fractional divider. This limits PLL granularity but is adequate for most calibration applications.

CHAPTER 7 — VERIFICATION

  1. Measure GPSDO output against WWV 10 MHz carrier using zero-beat method. Error should be <1 Hz.
  2. Confirm GPS lock: check satellite count in NMEA GPGGA sentence (≥4 sats required).
  3. Verify 1PPS LED or debug output shows TIMEPULSE active.
  4. Connect GPSDO to TinySA Ultra reference input (if equipped) and confirm TinySA frequency readouts are consistent with GPSDO.
  5. Log: date, firmware version, GPS module serial, lock time, frequency error.

APPENDIX A — CALCULATIONS AND FORMULAS

Si5351A output frequencyfout = fxtal × PLL_mult / (output_divider)
PPM error from integer counterrorppm = (fmeasured − 10,000,000) / 10
Allan deviation (GPSDO estimate)ADEV(τ = 1 s) ≈ 1×10−9 (crystal limited)

APPENDIX B — EXAMPLE RESULTS

GPSDO Lock and Stability Log
Time After Power-OnGPS Sats10 MHz FrequencyDeviationPLL State
0 min0——Acquiring
2 min5——Fix, no PLL
5 min89.999998 MHz−0.2 HzPLL locking
15 min910.000000 MHz<0.05 HzLocked
1 hour910.000000 MHz<0.02 HzStable
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