Merv's Brain Dump

Chapter 1 — Introduction and Scope

This manual covers the design, construction, and maintenance of a 12.8V nominal (4S LiFePO4) battery management system for field operation of amateur radio stations. The BMS uses a Texas Instruments BQ76920 IC for cell voltage monitoring, overcharge/overdischarge/overcurrent protection, and passive cell balancing. A secondary discrete comparator circuit provides backup protection. Optional MPPT integration enables solar charging.

Pack specifications: 12.8V nominal (10.0–14.4V operating range), 50 A maximum continuous discharge, 25 A maximum charge.

SAFETY — LITHIUM BATTERY HAZARD: LiFePO4 cells are safer than other lithium chemistries but still present fire and explosion risk if shorted, overcharged, or mechanically damaged. Never short the pack terminals. Never charge below 0°C. Never disassemble a swollen cell.

Chapter 2 — Theory of Operation

2-1 LiFePO4 Cell Parameters

LiFePO4 (lithium iron phosphate) cells have a flat discharge curve from approximately 3.05V to 3.30V, covering 20%–80% SOC. Key voltage limits:

2-2 BQ76920 Protection IC

The BQ76920 monitors each cell individually via its internal 14-bit ADC (1.22 mV resolution, 1% accuracy). It drives separate CHG (charge) and DSG (discharge) MOSFET outputs for independent control of charging and discharging. Communication via I2C allows the ESP32 host to read cell voltages, set protection thresholds, and enable/disable balancing FETs.

2-3 Cell Balancing

Passive balancing dissipates excess energy from the highest-voltage cells via internal 10 A balancing FETs (10Ω resistors, ~130 mW per cell at 3.6V). Active balancing transfers charge from high cells to low cells using a flyback or capacitor-based converter; more efficient but more complex. Passive balancing is adequate for matched cells with <50 mV initial spread.

Chapter 3 — Equipment and Materials

Chapter 4 — Construction

1. Connect cells in series (4S): Cell 1 (-) to pack negative; Cell 4 (+) to pack positive through the BMS FETs. Use copper bus bars (≥8 AWG equivalent) for all cell interconnects.
2. Solder the BQ76920 sense wires to each cell junction: VC0 to pack (−), VC1 to Cell 1/2 junction, ..., VC4 to pack (+). Keep sense leads <100 mm; twist in pairs; add 1kΩ series resistors to protect the BQ76920 inputs.
3. Install CHG and DSG MOSFETs on a common heatsink (thermal resistance ≤2°C/W for 50 A continuous). Connect gate drives from BQ76920 CHG and DSG outputs via 100Ω gate resistors.
4. Install the current sense resistor (5 mΩ) in series with the discharge path negative bus. Connect BQ76920 SRP and SRN to each side.
5. Connect ESP32 I2C (SCL, SDA, 4.7 kΩ pull-ups to 3.3V) to BQ76920 SCL/SDA pins.

Chapter 5 — Operating Procedures

1. First charge: connect a 14.6V constant-voltage charger (LiFePO4 profile, CC/CV). Monitor all four cell voltages on the CYD display during the first charge cycle. If any cell exceeds 3.65V before the others reach 3.45V, the pack is unbalanced — stop and balance manually.
2. Normal operation: the CYD displays pack voltage, current, SOC (from Coulomb counting), and individual cell voltages. SOC warning at 20%; shutdown at 10% (10.0V).
3. Temperature limits: if any cell or FET temperature exceeds 55°C during discharge, reduce load. Charging is inhibited below 0°C by firmware.

Chapter 6 — Calibration

1. Calibrate cell voltage offsets: measure each cell with a precision DMM (Fluke 15B+). Compare to BQ76920 I2C readings. Enter offset corrections in firmware NVS (ESP32 Preferences library).
2. Calibrate current sense: apply a known load (resistive, measured with the calibrated DMM). Adjust firmware current-sense gain constant until displayed current matches measured.
3. Calibrate SOC: fully charge pack to 14.4V. Reset Coulomb counter to 100%. Discharge completely to 10.0V. Record Ah removed. Compare to cell rated capacity. Adjust C_nominal in firmware.

Chapter 7 — Verification and Acceptance

1. All cell voltages within 20 mV of each other at rest (balanced).
2. OV protection: charge one cell to 3.70V (using external bench supply on sense pins). Verify BQ76920 opens CHG FET within 2 seconds.
3. UV protection: discharge to 9.8V. Verify DSG FET opens within 1 second.
4. Overcurrent: apply a momentary 60 A load for 100 ms. Verify DSG FET opens (BQ76920 OCD detection).
5. Log: date, cell batch numbers, initial balance spread (mV), OV trip voltage, UV trip voltage, OCD trip current, measured capacity (Ah), operator.

Appendix A — LiFePO4 State of Charge vs. Voltage

Note: LiFePO4 voltage vs. SOC is very flat from 20%–80%. Coulomb counting is more accurate than voltage for SOC estimation in this range.

Appendix B — BQ76920 Key I2C Registers